There is a class of semiconductor devices in which a gate electrode is formed in a trench that extends from the surface of a semiconductor chip. One example is a trench-gated MOSFET, and other examples include insulated gate bipolar transistors (IGBTs), junction field-effect transistors (JFETs) and accumulation-mode field-effect transistors (ACCUFETs). All of these devices share the common characteristic of a trench structure where the bottom of the trench for some reason can be exposed to high electric fields or where the bottom of the trench might form a parasitic capacitor including the gate electrode and the semiconductor material surrounding the trench.
FIGS. 1 through 10 show cross-sectional views and characteristics of known trench-gated devices. FIG. 1 shows a trench-gated MOSFET 100 having a top metal layer 102, a gate 104 formed in a trench 106 and separated from an epitaxial silicon layer 108 by a gate oxide layer 110. MOSFET 100 also includes an N+ source region 112 and a P-body 114. The drain of MOSFET 100 includes the N-epi layer 108 and an N+ substrate 116. A deep P+ region 118 is created under P-body 114, as suggested in U.S. Pat. No. 5,072,266 to Bulucea et al. The PN junction between deep P+ region 118 and N-epi layer 108 forms a voltage-clamping diode 117 where avalanche breakdown normally occurs. A P+ body contact region 119 forms a contact between metal layer 102 and P-body 114. The gate, which is typically formed of polysilicon, is protected from the metal layer 102 by an oxide layer 120 that is above the gate 104 and that is patterned with a feature that does not correspond to the trench itself, typically a contact mask.
As shown, gate oxide layer 110 consists of a uniform thin layer of oxide along the three sides of the polysilicon gate 104. That is, the portions of gate oxide layer 110 on the sidewalls of the trench and also the curved and linear portions of the gate oxide layer 110 at the bottom of the trench (except for some stress-related and etch-related changes in the oxide thickness that occur at the trench bottom) are generally of a uniform thickness in the range of, for example, 150 Å to 1,200 Å.
There are many variations of this general type of MOSFET. For example, FIG. 2 shows a MOSFET 130 which is generally similar to MOSFET 100 but does not include a deep P+ region 118. The gate of MOSFET 130 protrudes slightly through P-body 132 because the depth of P-body 132 and the depth of the trench 134 are determined in two unrelated processes. Thus, in vertical devices there is no guarantee of the net overlap of the polysilicon gate into the drain region. It turns out that this variation affects the operation of the device and may affect its reliability as well. Also, in FIG. 2 there is no additional diode formed by the deep P+ region 118 to clamp the voltage, so breakdown can occur wherever the voltage is raised to the point that the device goes into avalanche.
MOSFET 140, shown in FIG. 3, is variation of MOSFETs 100 and 130, where the MOSFET cells 142 contain no deep P+ region, and a diode cell 144 containing a deep P+ region is distributed at predetermined intervals throughout the array to act as a voltage clamp and limit the strength of the electric fields in the MOSFET cells. In MOSFET 140, the gate oxide layer is of uniform thickness.
FIGS. 4A–4G illustrate various aspects of the breakdown phenomenon. FIG. 4A shows the electric field strength contours at breakdown in a trench-gated device 150 having a relatively thick gate oxide layer. Device 150 is in effect a gated diode, a structural element of most trench-gated vertical power MOSFETs. As indicated, the strongest electric field, where impact ionization would occur during avalanche breakdown, is located at the junction directly beneath the P+ body region. In contrast, device 160, shown in FIG. 4B, has a relatively thin gate oxide layer. While some ionization still occurs underneath the P+ region, the highest electric field levels are now located near the corner of the trench. A field plate induced breakdown mechanism causes the strength of the electric field to increase.
FIGS. 4C and 4D show the ionization contours of devices 150 and 160, respectively, when they go into avalanche breakdown. Whether there is a thick gate oxide layer, as in FIG. 4C, or thin gate oxide layer, as in FIG. 4D, eventually in “deep” avalanche, i.e., when the device is forced to conduct large currents in avalanche, breakdown starts to occur at the corner of the trench. Even in the thick oxide case (FIG. 4C), where the peak electric field is not at the corner of the trench (FIG. 4A), as the drain voltage increases eventually ionization occurs at the corner of the trench. However, there are more contours in FIG. 4D, indicating a higher ionization rate where the gate oxide layer is thin.
FIG. 4E shows that if one introduces a diode clamp including a deep P+ region, as shown on the right-hand side, the diode will break down at a lower voltage, and avalanche breakdown should not occur at the corner of the trench. If the resistance of the current path through the diode is low enough, then the diode will clamp the maximum voltage of the device. As a result, the voltage will never rise to the point that avalanche breakdown occurs near the corners of the trenches.
FIG. 4F is a graph showing the breakdown voltage (BV) as a function of gate oxide thickness (XOX) for 20 V and 30 V devices. The doping concentration of the epitaxial (epi) layer in the 30 volt device is more lightly doped. The 30 V device would ideally have an avalanche breakdown of around 38 volts. In the 20 volt device the epi would be more heavily doped and the device would ideally have an avalanche breakdown of around 26 or 27 V. As the gate oxide is thinned from 1,000 Å to a few hundred Å, basically the breakdown voltages are relatively constant or may actually even increase somewhat as the shape of the field plate of the gate is actually beginning to help relax the electric field. At thicknesses of less a few hundred Å, however, breakdown degradation begins to occur.
Beyond the point where the breakdown voltage begins to drop (below 30 V for the 30 V device epi and below 20 V for the 20 V device) is the area labeled field plate induced (fpi) breakdown. In this area, breakdown occurs near the trench. For a reliable device one needs to add a diode clamp having a breakdown that is lower than the breakdown in the field plate induced area, so that the diode breaks down first. With a diode having a breakdown voltage as shown in FIG. 4F, breakdown would never occur near the gate in the 30 V device, but that diode would have too high a breakdown voltage to protect a 20 V device. To protect the 20 V device, the breakdown voltage of the diode clamp would have to be below the curve for the 20 V device.
FIG. 4G is a schematic diagram of the devices shown in FIGS. 4A–4D showing a gated diode in parallel with a MOSFET and a diode voltage clamp in parallel with both the MOSFET and gated diode. The arrangement is designed such that the diode clamp breaks down first. The gated diode never “avalanches” before the diode clamp. This becomes more and more difficult to do as the gate oxide layer becomes thinner.
FIGS. 5A and 5B show the ionization contours in a device 170 having a sharp trench corner and a device 172 having a rounded trench corner. FIG. 5B indicates that rounding the trench corners does reduce the magnitude of the ionization, but ultimately if one drives the device deeply enough into breakdown, the breakdown still occurs at the trench corner, and the device is at risk.
FIGS. 6A–6C show the electric field strength contours, the equipotential lines and the electric field lines, respectively, in a MOSFET 180. The gate of MOSFET 180 is tied to the source and body and is grounded, and the drain is biased at VD. From FIG. 6B it is evident that the drain voltage VD is divided and spaced out across the region. On the left hand side of FIG. 6B, the equipotential lines are squeezed closer together, and particularly around the trench corner they are squeezed even tighter. This produces electric field lines that are at right angles to the equipotential lines, as shown in FIG. 6C. One can see why a high electric field occurs at the trench corner and why rounding the corner does not solve this problem. It is basically a volumetric problem in that there is an electric field that terminates on an electrode having a lower surface area, namely the gate, and so the electric field lines are crowded at the corner.
FIG. 6D shows MOSFET 180 when it is turned on by putting a positive voltage VG on the gate. A current flows down the side wall of the trench and then it also spreads out along the bottom of the trench and into the region below the mesa at an angle from the side of the trench. However, in the process the current flows through areas that have high electric fields, as shown by the electric field contours of FIG. 6A. When a high current flows through an area that has a high field (and that would be the case where the device is saturated), the current carriers collide with the atoms of the epi layer and knock off, by momentum transfer, additional carriers. This forms new electron-hole pairs that in turn are accelerated and create additional collisions, ionizing additional atoms.
FIG. 6E shows the ionization contours in MOSFET 180 when it is in the on state. The ionization contours shown in FIG. 6E are different from those shown in FIG. 4C, for example, when device 150 is in the off state. The difference is that the ionization contours pull upwards all the way around the side of the trench, even up near the P-body. This has a number of damaging effects on the device. One effect is that it creates electron-hole pairs in the vicinity of the gate oxide that can be accelerated quite easily by the high electric field in that area. The electron-hole pairs can actually be trapped in the gate oxide, and they can damage the gate oxide.
Furthermore, this phenomenon produces an upper limit in the amount of voltage that one can put on the device, because so many electron-hole pairs may be produced that they begin to modulate the effective doping concentration of the epitaxial layer, by making the region around the side of the trench seem more heavily doped than it actually is. That occurs because electrons from the newly generated electron-hole pairs are swept into the substrate by the positive drain voltage VD, and the holes are swept into the P-body. The net effect is that, since the electrons and holes can only travel at a certain velocity, the local charge distribution adjusts itself to maintain charge neutrality. Specifically, surrounding the reverse-biased junction is a region known as a depletion region or space charge region, where (in the absence of impact ionization) no free charge carriers are present. The immobile charge residing within the depletion region, namely positive ions on the N-type side of the junction and negative ions on the P-type side of the junction, produces a “built-in” electric field across the junction. In the presence of impact ionization, the holes drifting across the N-type region add to the positive fixed charge and thereby increase the electric field, further enhancing the impact ionization process. These excess holes make the epitaxial region, which in this example is N-type material, appear more heavily doped because of the increase in the “built-in” field. The net effect is an increase in the electric field, which degrades the breakdown. This effect is shown in the current-voltage characteristics of FIG. 6F where the drain current ID increases dramatically at a certain drain voltage. The drain voltage at which this happens is the same for each of the gate voltages shown. This problem becomes worse as the gate oxide is thinned.
Another problem with the trench device relates to capacitance. FIG. 7A is a schematic diagram of a MOSFET 190 having a gate driven by a current source 192 and having resistive load 194. A voltage source 196 connected to the source and drain supplies a voltage VDD resulting in a drain voltage VD at the drain. As shown in FIGS. 7B–7D, at a time t1 current source 192 begins to supply a constant current to the gate and the voltage on the gate relative to the source, labeled VG in FIG. 7C, starts to rise. But because it does not immediately hit threshold, the drain voltage VD does not start to fall because MOSFET 190 is not yet turned on. As soon as the VG hits threshold, at time t2, MOSFET 192 saturates and turns on and carries current. VD starts to drop, but as it starts to drop it causes a capacitive coupling between the drain and the gate of MOSFET192 and halts the upwards progression of the gate voltage VG. VG remains flat until MOSFET 192 gets into its linear region. Then, MOSFET 192 begins to look like an on-resistance in a voltage divider, with a small voltage across MOSFET 192 and most of the voltage VDD across resistor 194.
At that point the capacitive coupling effect between gate and drain is satisfied and the VG continues its progress to a higher voltage. The plateau is due to a gate-to-drain overlap capacitance similar to the Miller effect, but this is not a small signal effect. This is a large signal effect. At that time the drain current ID also continues to rise, but as shown in FIG. 7D its upward progression is slowed.
FIG. 7E shows a plot of VG as function of the charge on the gate QG, where QG is equal to IG times the time t, IG being a constant. The gate voltage VG rises to a certain level, then it remains constant, and then it rises again. If there were no feedback capacitance between the drain and gate, the voltage would rise linearly, but instead the straight line is interrupted by the plateau.
In FIG. 7E, the point VG1, QG1 corresponds to a certain capacitance because C is equal to ΔQ over ΔV. Since it takes more charge to get to the point, QG2 and VG1, then that point reflects more capacitance. So the capacitance in the device, as shown in FIG. 7F, starts at a low value CISS, which is relatively constant, and then it jumps to a higher effective value CG(eff), and then it is relatively constant. Because of this effect the device has a higher effective capacitance than is desirable during the switching transition. As a result, there is an undue amount of energy lost in turning the device on.
As shown in FIG. 7G, the input capacitance actually has a number of components, including the gate-to-source capacitance CGS and the gate-to-body capacitance CGB, neither of which exhibits the amplification effect of the gate-to-drain capacitance CGD. The gate-to-drain capacitance CGD is shown in FIG. 7G, around the bottom and side wall of the trench. The equivalent schematic is shown in FIG. 7H. Even if CGD is the same order of magnitude as CGS and CGB, electrically it will look much larger (e.g., 5 to 10 times larger) because it is amplified during the switching process.
As indicated above, rounding the trench bottom helps to limit the damage to the gate oxide layer, although it is not a complete solution to the problem. FIGS. 8A–8C illustrate a process for forming a trench with rounded corners. In FIG. 8A small reaction ions 202 etch the silicon through an opening in a mask 200 at the surface. Ions 202 are accelerated by an electric field in a downward direction such that they etch a trench having essentially a straight side wall. When the trench reaches a certain depth the electric field is relaxed, as shown in FIG. 8B. Alternatively, one could possibly change the chemistry. At the end of the process, as shown in FIG. 8C, the electric field is modified so that the etching ions are traveling in all different directions. That begins to not only widen the trench, but also rounds out the bottom. Hence, the process includes an anisotropic etch that is converted to an isotropic etch. The anisotropy is also influenced by the formation of a polymer as a by-product of the etching operation on the sidewall of the trench. If the chemistry removes the polymer as soon as it forms, the etch will behave in a more isotropic way. If the polymer remains on the sidewall, only the bottom of the trench will continue to etch.
FIGS. 9A–9D show a method that includes creating a mask 210 (FIG. 9A), etching the trench 212 (FIG. 9B), forming an oxide layer 214 on the walls of the trench (FIG. 9C), which may be removed and then re-grown to remove defects (this is called sacrificial oxidation), and then filling the trench with a polysilicon layer 216 (FIG. 9D).
FIGS. 10A–10F illustrate a typical process of forming a trench MOSFET. The process starts with an N-epitaxial layer 220 grown on an N+ substrate 222 (FIG. 10A). Using the process of FIGS. 9A–9C, for example, a polysilicon-filled trench 224 is formed in N-epi layer 220 (FIG. 10B). The surface may or may not be planar depending on how the surface oxides are made in the process. Then a P-body 226 is introduced, although the P-body 226 could be introduced prior to the formation of the trench 224 (FIG. 10C). Both process flows are manufacturable, but forming the trench first is preferable because the etching process can influence the doping concentrations in the P-body. Then the surface is masked and an N+ source region 228 is implanted (FIG. 10D). An optional shallow P+ region 230 is implanted to ohmic contact between the P-body and a metal layer to be deposited later. P+ region 230 can be implanted through an opening in an oxide layer 232 that is deposited across the region and then etched to form a contact mask (FIG. 10E). The contact mask may or may not be used to define the P+ region 232. Finally, a metal layer 234 is deposited on the surface to contact the N+ source region 228 and P+ region 230 (FIG. 10F).